Gumstix

The Gumstix Verdex Pro XM4 is a PXA270-based motherboard with the following characteristics:

• Marvell® PXA270 Processor with XScale™
• 400MHz
• 64MB RAM
• 16MB Flash
• 60-pin Hirose I/O connector for extra connections
• 80-pin Hirose I/O connector for expansion boards connections
• 3.6V - 5.0V (max. 6.0V) supply voltage

The 60-pin Hirose connector has the following structure:

Pin	GPIO	Signal	Signal	GPIO	Pin
1		GND	GND		60
2	GPIO(67)	L_DD09	USBH_N2		59
3	GPIO(77)	L_BIAS	BITCLK	GPIO(28)	58
4	GPIO(61)	L_DD03	L_PCLK	GPIO(76)	57
5	GPIO(30)	SDATA_OUT	L_DD15	GPIO(73)	56
6	GPIO(66)	L_DD08	L_DD14	GPIO(72)	55
7		GND	FF_RXD	GPIO(34)	54
8	GPIO(71)	L_DD13	L_DD07	GPIO(65)	53
9	GPIO(70)	L_DD12	L_DD05	GPIO(63)	52
10	GPIO(69)	L_DD11	L_DD10	GPIO(68)	51
11		USBH_P2	L_DD01	GPIO(59)	50
12	GPIO(46)	IR_RXD	NACRESET	GPIO(113)	49
13	GPIO(60)	L_DD02	IR_TXD	GPIO(47)	48
14	GPIO(100)	FF_CTS	L_DD04	GPIO(62)	47
15	GPIO(9)	CLK_32	SYNC	GPIO(31)	46
16	GPIO(75)	L_LCLK	SSPRXD2	GPIO(11)	45
17	GPIO(17)	PWM1	SSPSFRM2	GPIO(14)	44
18	GPIO(58)	L_DD00	SDATA_IN0	GPIO(29)	43
19	GPIO(118)	I2C_SDA	GND		42
20	GPIO(117)	I2C_SCL	L_FCLK	GPIO(74)	41
21	GPIO(19)	SSPSCLK2	L_DD06	GPIO(64)	40
22	GPIO(87)	L_DD17	FF_RTS	GPIO(27)	39
23	GPIO(13)	SSPTXD2		GPIO(101)	38
24	GPIO(41)	OTG_ID	N_MANUAL_RESET		37
25	GPIO(2)	SYS_EN	PWM0	GPIO(16)	36
26	GPIO(39)	FF_TXD	BT_TXD	GPIO(43)	35
27	GPIO(86)	L_DD16	BT_RTS	GPIO(45)	34
28		V_BATT	BT_RXD	GPIO(42)	33
29		V_BATT	BT_CTS	GPIO(44)	32
30		V_BATT	GND		31

where:

Pins 28-29-30 are responsible for powering the net of boards. Expansion boards such as the netpro-vx have powering plugs. If powered, they provide energy for the net board itself as well as for the verdex connected to it and all other boards connected to the verdex. As we are using, besides the expansion boards and verdex, general purpose boards, here called TORP boards, the powering for the whole board network will be provided by the TORP board through pin 30.



Pins 1,7,31,42 and 60 are GND pins that should be provided by the TORP boards, as occurs for VCC.

LCD_Pins there are 22 pins that can be used to control LCD functions. When the LCD controller is disabled, all of its pins can be used for general-purpose input/output (GPIO).
  * Pin 57: L_PCLK - LCD Pixel Clock
  * Pin 16: L_LCLK - LCD Line Clock. It is a control signal that specifies command or data transactions when interfacing to an LCD panel with internal frame buffer.
  * Pin 41: L_FCLK - LCD Frame Clock. Read signal during reads from the panel with internal frame buffers. Write signal for writing to LCD panels with internal frame buffer.
  * Pin 3: L_BIAS - LCD Bias Drive. AC bias that signals the LCD display module to switch the polarity of the power supplies to the row and column axis of the screen to counteract DC offset. In active (TFT) mode, it is used as the output-enable to signal when data should be latched from the data pins using the pixel clock.
  * Data lines that transmit 4, 8, 16 or 18 data values at a time to the LCD display module. LDD<7:0> are used as an input data bus during reads from the panel with internal frame buffers. The following pins are used to send LCD data:
   - Pin 18: L_DD00
   - Pin 50: L_DD01
   - Pin 13: L_DD02
   - Pin 4: L_DD03
   - Pin 47: L_DD04
   - Pin 52: L_DD05
   - Pin 40: L_DD06
   - Pin 53: L_DD07
   - Pin 6: L_DD08
   - Pin 2: L_DD09
   - Pin 51: L_DD10
   - Pin 10: L_DD11
   - Pin 9: L_DD12
   - Pin 8: L_DD13
   - Pin 55: L_DD14
   - Pin 56: L_DD15
   - Pin 27: L_DD16
   - Pin 22: L_DD17

USB_Pins USBH_P2 and USBH_N2 are the differential signals of the USB ports.
 * Pin 11: USBH_P2 - D+
 * Pin 59: USBH_N2 - D-
The USB connector contains four wires: two to supply power (VBUS and GND) and two to move the USB data (D+ and D-). The VBUS wire provides 5V of power up to 500mA. The D+ and D- signals are bidirectional and their signaling voltage is 3.3V.

IrDA_Pins there are 2 pins that regulate infrared data transferring:
 * Pin 48: IR_TXD Transmit pin for fast infrared port
 * Pin 12: IR_RXD Receive pin for fast infrared port

UART_Pins there are 3 different logic level UARTs that can be used in the verdex pro: FFUART, BTUART and STUART.
 * FFUART is a UART with logic level (3.3V) signals, speeds to 230 kbps that is normally mapped to ttyS0 in the kernel and Y0 in some schematics. FFUART pins are:
   - Pin 14: FF_CTS Clear to send signal. Check PXA270 manual for detailed operation modes.
   - Pin 39: FF_RTS Request to send signal.Check PXA270 manual for detailed operation modes.
   - Pin 26: FF_TXD Serial data input
   - Pin 54: FF_RXD Serial data output

 * BTUART is a UART with logic level (3.3V) signals, that is not an exposed interface, mapped to ttyS1 by the kernel and connected physically to the bluetooth module if one is present. BTUART pins are:
   - Pin 32: BT_CTS Clear to send signal. Check PXA270 manual for detailed operation modes.
   - Pin 34: BT_RTS Request to send signal.Check PXA270 manual for detailed operation modes.
   - Pin 35: BT_TXD Serial data input
   - Pin 33: BT_RXD Serial data output
   - Pin 24: OTG_ID Determines whether the pins are acting as a host or a device.

 * STUART is a UART with logic level (3.3V) signals, speed up to 230 kbps that is normally mapped to ttyS2. STUART pins are:

SSP_Pins there is a Synchronous Serial Protocol port available in verdex pro. Its pin specification is as follows:
 * Pin 21: SSPSCLK2 Serial bit-clock to control the timing of a transfer. SSPSCLK2 is generated internally (master mode) or is supplied externally (slave mode)
 * Pin 23: SSPTXD2 Transmit data (serial data out) serialized data line
 * Pin 45: SSPRXD2 Receive data (serial data in) serialized data line
 * Pin 44: SSPSFRM2 Serial frame signal that indicates the beginning and the end of a serialized data word. SSPSFRM2 is generated internally (master mode)
or is supplied externally (slave mode).

AC97_Pins The AC ’97 controller supports the Audio Codec '97 Component Specification1, Revision 2.0. The AC-link is a synchronous, fixed-rate serial bus interface to the digital AC ’97 controller for transferring digital audio, modem, microphone input (MIC-in), Codec register control, and status information. The AC'97 pin in the verdex pro are:
 * Pin 43: SDATA_IN0 Serial audio input data from primary Codec
 * Pin 5: SDATA_OUT Serial audio output data to Codec for digital-to-analog conversion
 * Pin 58: BITCLK 12.288-MHz bit-rate clock (input pin)
 * Pin 49: NACRESET Active-low Codec reset. The Codec’s registers are reset when it is asserted
 * Pin 46: SYNC 48-kHz frame indicator and synchronizer

PWM_Pins there are 2 different PWM channels in verdex pro. PWM pins are:
 * Pin 36: PWM0 pwm output for channel 0
 * Pin 17: PWM1 pwm output for channel 1

SYS_EN_Pin Pin 25 is a special feature pin that cannot be used as GPIO. In the processor, it is the Power Capacitor pin. It must be connected to external capacitors to achieve very low power in sleep mode.

N_MANUAL_RESET_Pin Pin 37 used to trigger hard reset (power-on reset).

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